It now supports the assessment of the effects of spatial Multi-Bit Upsets (sMBUs) of different cardinalities and geometries in all hardware structures of modern CPUs modelled on gem5. This extra feature reflects the need to consider sMBUs and their impact on modern semiconductors. The tool has been also enhanced to provide detailed report about the masking effects of the different layers of a computing system stack (hardware-only, software-only and combined) to facilitate early-stage design decisions for error protection in CPUs. The unprecedented throughput of GeFIN in the analysis of long workloads and the accuracy of the reported full-system measurements make it the ideal framework for SoC architects and software developers in their decision-making process. It is available at very early design stages when system modifications are still cost-effective but it also provides assessments which are aware of the details of the most important hardware structures in the CPUs.