The SME's successfully applied for the second TETRAMAX Bilateral Technology Transfer call, proposing the HS-CHAR: High Speed Characterization of Mass Storage Devices project, which started in June 2019 and closes in December 2019.

The utilization of solid-state storage devices is rocketing, driven by data centers, artificial intelligence applications, autonomous drive and other fields where large data volume high computational power and low energy consumption are required. The core of the solid-state storage is the NAND technology, combining high density, fast access, low power and non-volatilit, but they are far from perfect. Their inherent failure modes include read errors, limited endurance and cell interference.

The SME NplusT develops and markets the NanoCycler equipment, especially created for NAND characterization. In this project they wanted to extend its product line with a new technology, targeting the high-speed characterization of non-volatile memory (NVM) devices, a feature essential for mass storage (SSD,...) makers in the optimization of their products. The other partner, PCBDesign, transferred its high-speed communication technology, in order to follow the NVM roadmap: increased density, higher speed, lower voltages.

Now the project has come to an end, it successfully characterized the prototype and transferred the specific technology to the NplusT engineering team. During the execution, several critical technology issues were addressed, including signal integrity, picosecond level fine tuning of the signal delays using FPGA, and algorithms to separate interface failures from real device failures. The early feedback from the market also demonstrates the validity of the project. The upgraded NanoCycler technology is leader in the NAND characterization, where high performance device management requires to be merged with accurate temperature control and scalability – at a reasonable price.

The new technology will be the core of further solutions on NplusT’s roadmap as a development environment for SSD firmware engineers and high parallelism reliability test systems.