Offer #2018.8

Fault recovery mechanism for FPGAs

Jožef Stefan Institute

The problem/challenge

The application of SRAM-based field-programmable gate arrays (FPGAs) in mission-critical systems requires error mitigation and recovery techniques to protect them from the errors caused by high-energy radiation, also known as single event upsets (SEUs). JSI has developed a low area-overhead SEU recovery mechanism that can be applied in different self-recoverable architectures. A fault-emulation environment enables the user to inject faults at selected locations of the configuration memory and experimentally evaluate the reliability of the developed solutions.

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Date published04/19/2018StatusLooking for collaborationTechnology areasDependable and Fault Tolerant SystemsReconfigurable ComputingSafety Critical Applications