In software-defined networking (SDN), the packet parsing is challenging due to the complexity of the protocols and for the need of flexibility not only for a variety of currently used network protocols but also new ones, to remain future proof.
We are working on programmable packet processing technology. The offer considers an advanced parser that is not needing TCAM for implementation. We have synthesized the designs on FPGA and on 28 nm ASIC technology. Based on the results, we are 4-5x smaller than the state-of-the-art parsers, and can support 1 GHz clock frequency on ASIC. The architecture is parallel, resembling VLIW processors on data processing side.
Switch and/or router equipment manufacturers. Mobile and fixed network equipment companies. OEMs interested in 5G compatibility.
Technology licensing and transfer of existing parser technology. Option for further research and development contracts on the parser and the following match-action pipeline processing that we are also working on.