Offer #2019.43

Dual Data Rate Network On Chip architecture

The problem/challenge

Performance of Network On Chip (“NoC”) can be improved as there is datapath underutilization. This is because typical NoC clock frequency in existing systems is defined by its control logic.

The invention/product

The invention is a novel Dual Data Rate NoC architecture with pipeline bypassing which routes packets at a rate defined solely by the data path of the NoC routers thereby maximizing performance.

Benefits include:

• Throughput Improvement 25% higher than state-of-the-art NoC architectures (at same energy consumption) Improves performance to cost ratio

• Latency Improvement Improved latency scalability (up to a 6x6 2D-mesh network size comparable; beyond that competitive). Improves performance to cost ratio

• Reduced Energy Consumption The processor chip consumes 1/3 of the total energy expenditure The NoC consumes 10% to 25% of the chip energy DDRNoC reduces NoC energy consumption by 40% (per bit) at the same throughput Improves performance to cost ratio

Companies/industry we are looking for

We are seeking companies providing microprocessor and embedded SoC development and IP cores. Some examples include: Intel, ARM, Cavium, Infineon, EZChip, Synopsis, Cadence, Mentor Graphics, STMicro, Nvidia, Kalray, Technolution, etc.

Next steps/Activities

RTL implementation of the DDR NoC has been done. We also have verified by simulating post-place and routed netlist with back annotated delays using 28nm technology libraries. We are currently undertaking verification using 22nm wafer technology. We are looking for partners to perform a larger scale pilot trial together, as well as technology adoption.

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Date published06/11/2019StatusLooking for collaborationTechnology areasIntegrated Circuit Design