Magnetoresistive memory (MRAM) is an emerging technology to replace current memory technologies (SRAM, DRAM, flash). MRAM provides several advantages such as being non-volatile, fast access, no leakage, etc.
However, MRAM suffers from high latency and energy usage during write operations. This is especially critical for many emerging low power technologies, e.g., IoT sensor nodes, battery-powered embedded systems.
The French Centre National de la Recherche Scientifique (CNRS) and Inria jointly developed a complier-based approach to perform static analysis of program control flow graphs, and provide data mappings on non-volatile memory banks. The outcome is a drastically reduced dynamic energy consumption from efficient data allocation for Non-volatile Memory (NVM).
The approach has been validated analytically on a benchmark suite and up to 80% memory energy reduction has been shown, compared to usual data allocation approach (publication available upon request). The conducted experiments were based on NVM read/write energy models obtained from the existing related literature. Our solution can be exploited by using the static analysis in order to determine the lifetime of program variables, based on which the data to be stored in those variables will be efficiently allocated to NVM memory.
We are seeking partners working with Non-volatile Memory or designing low-power compute node architectures, as well as those who could collaborate to perform prototype testing.
We believe the next steps are to confirm the observed energy consumption reduction can be achieved in an embedded system prototype. The data allocation could be implemented in various ways, e.g., via multi-bank main memory or multi-bank scratchpad memories. Prototype can either be implemented in FPGA or ASIC processor. We are also open to applying for funding from TETRAMAX TTX calls to facilitate the technology transfer.