There is relatively high power consumption of single large memories if they are in "power ON“ mode all the time. By selecting dedicated memory blocks which can be selectively switched to low-power modes in an optimized manner, 60% energy reduction could be achieved.

We have developed an optimization method that automatically synthesizing the architecture of a heterogeneous memory subsystem that requires minimal power (energy) while meeting the application's performance requirements (thereby avoiding costly caches and run-time cache line replacement strategies).

By mapping software code and data to a set of dedicated memories, these memories can selectively be switched to low-power modes as much as possible. A tool set takes optimization results and implements them in the software code automatically (e.g. mangling of addresses, adding instructions for memory power mode switching).

Prototype tools in lab environment have successfully been applied to benchmark suites but not on real applications in the field.

Current results achieved have been funded from a research project in Germany. We are looking to be in a larger, funded R&D project with industry collaborators prefably on an EU level. Some issues we would like to address are ways to extend the technology to exploit and improve memory access patterns in multicore systems.

Both R&D projects, and industry-funded contract research.