University of Stuttgart
We offer methods and tools for automatically synthesizing the architecture of a heterogeneous memory subsystem that requires minimal power (energy) while meeting the application's performance requirements. By analyzing memory access patterns of known application(s), dedicated memory blocks are selected to best match the application's needs, thereby avoiding costly caches and run-time cache line replacement strategies.
Our technology is currently productive for single-core systems.
The method and tools are offered together with consulting/research services in the context of industry-funded contract research.
In the future, we will extend the technology to exploit and improve memory access patterns in multicore systems. We are open to making such contributions in funded research projects.